1. Field of the Invention
The present invention relates to the field of resistor-based memory circuits. More particularly, it relates to a method for accurately sensing the resistance value of a resistor-based memory cell, for example, an MRAM magnetic memory cell.
2. Description of the Related Art
A resistor-based memory, such as that depicted in FIG. 1, typically consists of a memory cell array 150 having intersecting row lines 100 and column lines 110 connected by resistors 120. A resistor-based memory such as, for example, a magnetic random access memory (MRAM), typically includes an array of resistor-based, magnetic memory cells.
A typical magnetic memory cell includes a layer of magnetic film in which magnetization is alterable and a layer of magnetic film in which magnetization is fixed or xe2x80x9cpinnedxe2x80x9d in a particular direction. The magnetic film having alterable magnetization may be referred to as a data storage layer and the magnetic film which is pinned may be referred to as a reference layer.
Typically, the logic state of a magnetic memory cell is indicated by its resistance which depends on the relative orientations of magnetization in its data storage and reference layers. A magnetic memory cell is typically in a low resistance state if the orientation of magnetization in its data storage layer is substantially parallel to the orientation of magnetization in its reference layer. A magnetic memory cell is typically in a high resistance state if the orientation of magnetization in its data storage layer is substantially anti-parallel to the orientation of magnetization in its reference layer.
A magnetic memory cell is usually written to a desired logic state by applying external magnetic fields that rotate the orientation of magnetization in its data storage layer. Typically, the orientation of magnetization in the data storage layer aligns along an axis of the data storage layer that is commonly referred to as its easy axis. External magnetic fields are applied to flip the orientation of magnetization in the data storage layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer depending on the desired logic state.
When the orientation of magnetization is flipped, the resistance of the memory cell is altered between two different values. One resistance value, e.g., the higher value, may be selected to signify a logic xe2x80x9cHIGHxe2x80x9d while the other resistance value, e.g., the lower value, may be selected to signify a logic xe2x80x9cLOW.xe2x80x9d
The value of each memory cell is determined by measuring the resistance value of the cell so as to determine whether the cell corresponds to a logic xe2x80x9cHIGHxe2x80x9d or logic xe2x80x9cLOW.xe2x80x9d This measuring process had been made difficult due to several factors.
First, there is typically little to no isolation between memory cells. For example, turning to FIG. 2, which depicts a smaller portion of the FIG. 1 memory array, if an array consists of 1024 rows and 1024 columns, i.e., approximately 1 million cells, and each cell contains a resistance of 1.2 Mxcexa9 or 800 Kxcexa9, depending on its logic state, the measured resistance when all rows and all columns, except for those associated with the selected cell, are respectively shorted together (e.g., during a read operation as depicted by dotted lines in FIG. 1) will be approximately 1 xcexa9, leaving very little isolation between cells. Low isolation renders the measuring of the resistance value of a particular memory cell difficult. Currently available solutions to the isolation problem include inserting a metal oxide semiconductor field effect transistor (MOSFET) or a diode in the memory cell in order to change the resistance value, malting it easier to detect. This solution is overly complex, increases the size of the memory cell and complicates the manufacturing process.
Turning now to FIG. 3, a typical resistance sensing circuit is depicted. The unknown parallel paths are represented by an equivalent resistance 300 of approximately 1 Kxcexa9. The resistive element 210 of the selected cell is 1.2 Mxcexa9. The column line 230 and the unused row lines are maintained at some known voltage. The current through the resistance 300 of the unused row lines is kept as close to zero as practical by maintaining a zero difference of potential across the resistance 300. The voltage across the 1.2 Mxcexa9 resistance 210 to ground (at node A) is then read. One of the problems associated with the FIG. 3 circuit is that it is very difficult to maintain a zero difference of potential across the unused resistors 300, and, therefore, there is always a non-zero current flow through resistance 300, thus affecting the voltage reading at node A and making the reading of resistance 210 difficult and unreliable. For example, if the difference of potential across points A and B, that is, across resistor 300, is 2 mV, then the current through resistance 300 is approximately 2 xcexcA and if the voltage at node A to ground is maintained at e.g., 2 V, the current through resistance 210 is approximately 1.7 xcexcA. Since the voltage differences between points A and B are not stable, the current through resistor 300 varies, thereby posing serious problems when reading the contents of a memory cell.
Another concern is that since the resistance values of each cell are so high (e.g., approximately 1 Mxcexa9), large (RC) time constants will be experienced in the parasitic paths (i.e., for the unused cells). As known in the art, these large RC constants increase the time required to read out the contents of a memory cell. For example, the inherent discharge times can be undesirably long when all of the rows, except for the one being read out, and columns are pre-charged to some voltage. Furthermore, large resistance variations are typically experienced from cell to cell depending upon the processing employed during manufacturing, thus leading to less reliability during the measurement process. At least for those reasons described above, a simplified, more reliable method of sensing the resistance value of a resistor-based memory cell is desirable.
The present invention overcomes the problems associated with the prior art and provides a simplified and reliable method for sensing the resistance value of a resistor-based memory cell. A current is driven through all unused row lines of a memory array while grounding the row line associated with the selected cell, thereby forcing the current through a comparatively low equivalent resistance (e.g., 1 Kxcexa9) and also through a comparatively high resistance (e.g., 1.2 Mxcexa9 or 800 Kxcexa9) of the selected memory cell. The voltage on the column line corresponding to the selected memory cell is then measured to ground. The voltage level corresponds to either one of two resistance values (i.e., signifying either a logic xe2x80x9cHIGHxe2x80x9d or a logic xe2x80x9cLOWxe2x80x9d).